The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, which can improve operation reliability by constantly regulating a time necessary for internal operations, and a method for operating the same.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells selected by addresses inputted together with the data.
As the operating speed of the system is increasing, the data processor requires the semiconductor memory device to input and output data at higher speed. For the purpose of high-speed data input and output, a synchronous memory device was developed. The synchronous memory device inputs and outputs data in synchronization with a system clock. However, because even the synchronous memory device could not meet the required data input/output speed, a double data rate (DDR) memory device was developed. The DDR memory device outputs or inputs data at falling edges and rising edges of the system clock.
The DDR memory device must process two data during one cycle of the system clock so as to input and output data at a falling edge and a rising edge of the system clock. Specifically, the DDR memory device must output data exactly in synchronization with the rising edge and the falling edge of the clock. To this end, a data output circuit of the DDR memory device outputs data in synchronization with rising and falling edges of the system clock.
Recently, many attempts have been made to increase address input/output speed as well as data input/output speed in semiconductor memory devices capable of processing a large capacity of data at high speed. In a conventional semiconductor memory device, an address is inputted together with an external command in synchronization with a rising edge of a clock. That is, the semiconductor memory device receives an external address and an external command one time during one cycle of an external clock, specifically in synchronization with a rising edge of an external clock. As the operating speed of the semiconductor memory device further increases, a new architecture was proposed which can receive an address two times during one cycle of an external clock.
Graphics double data rate version 5 memory devices are designed to receive addresses at a rising edge and a falling edge of an external clock. That is, the memory devices can receive the addresses two times during one cycle of the external clock. Thus, compared with the general DDR memory device, the number of address pins is reduced and the operating speed can be increased by connecting extra pins to a power voltage terminal or a ground terminal. Since an external command is inputted in synchronization with a rising edge of an external clock, the address input speed is two times faster than a command input speed.
FIG. 1 is a timing diagram illustrating a read operation and a write operation of a memory device.
Referring to FIG. 1, the memory device receives two addresses A1 and A2 during one cycle of a system clock HCLK in a read operation and a write operation, and inputs or outputs four data corresponding to the addresses during one cycle of the system clock HCLK. In the write operation, a write command WR and the addresses A1 and A2 are inputted at a time T1. The write command WR is inputted in synchronization with a rising edge of the system clock HCLK, and the addresses A1 and A2 are inputted in synchronization with a rising edge and a falling edge of the system clock HCLK. Since the memory device can receive the address two times during one cycle of the system clock HCLK, the number of address pins is reduced and the operating speed can be increased by connecting extra pins to a power voltage terminal or a ground terminal.
Data Q0 to Q7 for being outputted according to the write command WR and the addresses A1 and A2 inputted in synchronization with the rising edge or the rising and falling edges of the system clock HCLK are inputted into the memory device through data pads DQ[0:31] in synchronization with an output reference clock REF_CLK having a frequency two times faster than that of the system clock HCLK after a write latency elapses from the input of the write command WR. As described above, the output reference clock REF_CLK, instead of the system clock HCLK, is used as a reference of data input in order to input four data per one cycle of the system clock HCLK.
In the read operation, a read command RD and addresses A1′ and A2′ are inputted at a time T11. Data Q0 to Q7 corresponding to the addresses A1′ and A2′ are outputted through data pads DQ[0:31] after a read latency RL elapses from the input of the read command RD. In the read operation, the semiconductor memory device receives two addresses during one cycle of the system clock HCLK and outputs four data corresponding to the addresses during one cycle of the system clock HCLK.
As can be seen in the read operation and the write operation, the memory device uses two clocks, that is, a clock for the input/output of the command and the addresses and a clock for the input/output of the data. The two clocks have different frequencies from each other. More specifically, the clock for the input/output of the command and the addresses has half the frequency of the clock for the input/output of the data. In order to normally maintain the read latency and the write latency, that is, a time difference between the input of the command and the input/output of the data in the read operation and the write operation, the clock for the input/output of the data must be divided and adjusted to have the same phase as the clock for the input/output of the command and the addresses.
FIG. 2 is a timing diagram illustrating an internal operation of the semiconductor memory device for the read operation.
Referring to FIG. 2, the read command RD and the addresses A1 and A2 are inputted to the semiconductor memory device at a time t1 in synchronization with the system clock HCLK. The semiconductor memory device outputs data in synchronization with a data output clock WCLK having two times the frequency of the system clock HCLK. The semiconductor memory device performs a ½ frequency division with respect to the data output clock WCLK to generate divided output clocks WCLK_DV0 and WCLK_DV1.
The semiconductor memory device decodes the read command RD to generate an internal read command ICMD. The internal read command ICMD for data output is recognized in the internal circuits of the semiconductor memory device, based on the data output clock WCLK, not the system clock HCLK. As illustrated in FIG. 2, a read command strobe signal for recognizing the internal read command ICMD is synchronized with the divided output clocks WCLK_DV0 and WCLK_DV1, not the system clock HCLK. The divided output clocks WCLK_DV0 and WCLK_DV1 have the same period as the system clock HCLK because they are generated by the ½ frequency division of the data output clock WCLK having two times the frequency of the system clock HCLK. However, the divided output clock WCLK_DV0 has a phase equal to that of the system clock HCLK, while the divided output clock WCLK_DV1 has a phase different from that of the system clock HCLK.
Due to the read command strobe signal generated in synchronization with the rising edge of the divided output clocks WCLK_DV0 and WCLK_DV1, the read latencies RL1 and RL2 of the semiconductor memory device may be different from each other in the case where the divided output clocks WCLK_DV0 and WCLK_DV1 have a phase equal to that of the system clock HCLK and the case where the divided output clocks WCLK_DV0 and WCLK_DV1 have a phase different from that of the system clock HCLK. That is, a time from the input of the read command RD to the output of the data corresponding to the read command RD may change according to the phases of the divided output clocks WCLK_DV0 and WCLK_DV1 and the system clock HCLK. A difference (RL2−RL1) of the read latencies may be generated in the ½ frequency division of the data output clock WCLK, and it may degrade the operation reliability of the semiconductor memory device.
When there is a change in the read latency and the write latency defined in the specification defining the performance of the semiconductor memory device, a system with the semiconductor memory device may malfunction. Therefore, in order to ensure a stable operation, the semiconductor memory device must always constantly maintain the read latency and the write latency, that is, a time necessary to output data after the read and write commands are inputted.